Generally, electronic systems are implemented using integrated devices, discrete semiconductor devices, or combinations of both integrated and discrete semiconductor devices. For example, in power conversion circuits an integrated control circuit drives discrete power Field Effect Transistors (FETS) to generate an output voltage at a switching node. In manufacturing these types of circuits, electrical nodes are coupled together in such a fashion as to preclude safely testing functional parameters associated with the electrical nodes. FIG. 1 is a circuit schematic of a prior art semiconductor component 10. Semiconductor component 10 includes a high side FET 12 connected to a low side FET 14. More particularly, high side FET 12 has a drain coupled for receiving an input signal VIN, a source connected to a drain of low side FET 14 to form a phase or switching node 16, and a gate coupled for receiving a gate drive signal from a driver circuit 18. Low side FET 14 has a source coupled for receiving a source of operating potential VSS and a gate coupled for receiving a gate drive signal from driver circuit 18.
Driver circuit 18 includes a control circuit 20 having an input coupled for receiving a Pulse Width Modulation (PWM) signal, VPWM, an output connected to a gate driver 22, and another output connected to a gate driver 24. The output of gate driver 22 is connected to the gate of high side FET 12 and to a monitoring terminal GH. The output of gate driver 24 is connected to the gate of low side FET 14 and to a monitoring terminal GL. Gate drivers 22 and 24 have inputs or supply terminals 25 and 27 coupled for receiving a source of operating potential VDD. Gate driver 22 has an input 26 connected to node 16 and gate driver 24 has an input or supply terminal 28 coupled for receiving source of operating potential VSS.
FIG. 2 is a top view of prior art semiconductor component 10 that is partially packaged. More particularly, FIG. 2 illustrates FETS 12 and 14 and driver circuit 18 in chip form and mounted on a leadframe 30 that has been singulated. In practice, FETS 12 and 14 are formed from a semiconductor wafer in which a drain is formed from a major surface and a source is formed from an opposing major surface. Similarly, driver circuit 18 is formed from a semiconductor wafer having active and contact surfaces. The semiconductor wafers from which FETS 12 and 14 and driver circuit 18 are manufactured are comprised of a semiconductor material and are diced into semiconductor die or chips. Thus, FETS 12 and 14 and driver circuit 18 are in chip or die form. Because FETS 12 and 14 and driver circuit 18 are represented by the circuit schematics shown in FIG. 1 but realized in chip form, reference characters 12, 14, and 18 are used to refer to the devices in both chip form and schematically. For the sake of explanation, the mold compound used to protect FETS 12 and 14 and driver circuit 18 has been omitted from FIG. 2. Leadframe 30 is preferably a copper leadframe that has semiconductor chip receiving areas 32, 34, and 38 to which FETS 12, 14, and driver circuit 18 have been attached, respectively. In addition, leadframe 30 has a plurality of leadframe leads 50, 90, 91, 92, 94, 96, and 98. Semiconductor chip receiving areas 32 and 34 are spaced apart from each other by a region 40, semiconductor chip receiving areas 34 and 38 are spaced apart from each other by a region 42, and semiconductor chip receiving areas 32 and 38 are spaced apart from each other by a region 44. As those skilled in the art are aware, in the absence of a mold compound, regions 40, 42, and 44 are open regions and when mold compound is present regions 40, 42, and 44 are filled with the mold compound.
The drain of FET 12, i.e., the bottom major surface, is electrically coupled to semiconductor chip receiving area 32 and the drain of FET 14 is electrically coupled to semiconductor chip receiving area 34. The source of FET 12 is electrically coupled to semiconductor chip receiving area 34, and therefore to the drain of FET 14, by an electrically conductive clip 46. Thus, semiconductor chip receiving area 34 serves as node 16 shown in FIG. 1. The source of FET 14, i.e., the top major surface, is electrically coupled to leadframe fingers 50 by an electrically conductive clip 48. The portions of leadframe 30 underlying clips 46 and 48 are shown as broken lines.
Driver circuit 18 has bond pads 52, 54, 56, 58, 60, 62, 64, and 66 formed on the active surface of its semiconductor material. Bond pad 52 is coupled to gate bond pad 33 of FET 12 by bond wires 80 and to leadframe lead 91 by bond wire 88; bond pad 54 is coupled to down bonds 37 of semiconductor chip receiving area 34 by bond wires 83; bond pad 56 is coupled to gate bond pad 35 of FET 14 by bond wires 81 and to leadframe lead 90 by bond wire 82; bond pads 58 and 60 are coupled to down bond 39 of semiconductor chip receiving area 38 by bond wires 84; bond pad 62 is coupled to leadframe lead 92 by bond wire 85; bond pad 64 is coupled to leadframe lead 94 by bond wire 86; bond pad 66 is coupled to leadframe lead 96 by bond wire 87; and bond pad 31 is coupled to leadframe lead 98 by bond wire 89. A down bond is a region in a support structure to which bond wires are typically bonded.
It should be noted that leadframe leads 50 and 90 are spaced apart from semiconductor chip receiving area 34 by regions 100 and 102, respectively; leadframe lead 92 is spaced apart from semiconductor chip receiving area 38 by region 104; leadframe leads 94 and 96 are spaced apart from semiconductor chip receiving area 38 by region 106; and leadframe leads 91 and 98 are spaced apart from semiconductor chip receiving area 32 by region 108. Like regions 40, 42, and 44, regions 100, 102, 104, 106, and 108 are open regions in the absence of mold compound and filled with mold compound when it is present.
Leadframe leads 90 and 91 are used to monitor the voltages at the gates of FETS 12 and 14, respectively. Thus, they receive signals GH and GL shown in FIG. 1.
Testing parameters in a semiconductor component that includes an integrated driver circuit coupled to and packaged with a FET is more challenging than testing an individual integrated driver circuit and an individual FET. An example of a packaged semiconductor component that includes an integrated driver circuit coupled to a FET is a driver MOSFET, commonly referred to as an integrated DrMOS. In these types of circuits, there is a risk of damaging the driver circuit when tests that involve the drain-to-source voltage of the low side FET are near or exceed the absolute maximum rating of the driver circuit. For example, testing the avalanche breakdown voltage (BVdss) of low side FET 14 involves injecting a current into node 16, i.e., the drain of low side FET 14. When the current becomes sufficiently high, low side FET 14 breaks down into the avalanche region and the voltage at the input of gate drive circuit 22 exceeds the maximum rated voltage for bias input 26 resulting in gate drive circuit 22 becoming damaged. Similarly, it is very difficult to perform unclamped inductive switching (UIS) tests on integrated DrMOS devices when the drain-to-source voltages of low side FET 14 exceeds the avalanche breakdown voltage.
Performing an Idss leakage test is very difficult when the drain-to-source voltage of low side FET 14 is close to the absolute maximum of the driver circuit. Since the drain of low side FET 14 is connected to input 16 of gate drive circuit 22, the Idss leakage current of low side FET 14 cannot be measured with any degree of accuracy due to the presence of multiple current paths. With low side FET 14 directly connected to driver circuit 18, low side FET 14 interferes with any voltage applied on SWN node 16 by pulling it down when the voltage on pin GL goes high. Examples of other tests that cannot be performed when low side FET 14 is directly connected to driver circuit 18 include zero cross detect threshold, SWN pre-overvoltage threshold testing, and Power On Reset (POR) threshold tests.
Accordingly, it would be advantageous to have a structure suitable for measuring electrical parameters such as breakdown voltage BVdss and leakage current Idss in a low side FET without damaging driver circuitry coupled to the low side FET and a method for manufacturing the structure. It would be of further advantage for the structure and method to be cost efficient and suitable for standardized packaging configurations.